1. Field of the Invention
The present invention relates to electronic cameras. More particularly, the present invention relates to CMOS electronic cameras with electronic shutters and to an improved electronic shutter using buried layers.
2. The Prior Art
Electronic cameras using imaging arrays are known in the art. Both CCD and CMOS imagers have been employed in such cameras.
Some electronic cameras that employ CMOS active pixel sensors have employed such sensors equipped with an “electronic shutter” feature. The use of an electronic shutter is desirable because it eliminates the need for a mechanical shutter, reducing cost and complexity while improving the problem of latency between triggering an exposure and capturing an exposure. Electronic shutters in CMOS active pixel sensor arrays usually come in one of two forms: a rolling shutter or a true simultaneous shutter. A rolling shutter operates by successively exposing and resetting rows of pixels in the sensor. This type of shutter results in either a different total exposure time for pixels in different rows, or exposure to light from a scene at different points in time for the pixels in different rows. In either case, the resulting image can suffer from noticeable artifacts, particularly if objects in the scene are moving. A true simultaneous electronic shutter allows all pixels of the array to be exposed to incident light for the same period of time, thereby permitting an accurate and simultaneous snapshot of an entire scene. For quality images, a true simultaneous electronic shutter is the preferred method. The true simultaneous electronic shutter feature is usually implemented in CMOS active pixel sensors by providing a switching transistor disposed between the output of the photodiode photosensor and an amplifier associated with the pixel sensor.
Such an arrangement is shown in FIG. 1 in which photodiode 10 is shown coupled to reset transistor 12. The electronic shutter in the active pixel sensor of FIG. 1 is implemented as transistor 14, sometimes referred to as a transfer transistor, disposed between the cathode of photodiode 10 and the gate of the source-follower amplifier transistor 16. The source of source-follower amplifier transistor 16 is coupled to an output column line 18 of the array through a row-select transistor 20, whose gate is driven by one of the row lines 22 in the array.
As known in the art, the pixel sensor of FIG. 1 is operated by first turning on the reset transistor 12 to drive the cathode of photodiode 10 to a known potential. The transfer transistor is also turned on during this reset period to charge the gate of transfer transistor 16 (also referred to as the sense node) to a known voltage. When the reset signal at the gate of reset transistor 12 is de-asserted, integration of photo-generated charges begins. When it is desired to end the exposure, transfer transistor 14 is turned off. At this time, a signal voltage representing the accumulated photo-generated charge may be driven onto column line 18 by asserting a row-select signal on row-select line 22 and thereby turning on the row select transistor 20.
Large electric fields associated with the transfer transistor 14 in the active pixel sensor of FIG. 1 cause undesirable leakage paths (shown as dashed-line resistors 24 in FIG. 1) and the relatively large capacitances (shown as dashed-line capacitors 26) inherent in the circuit cause reduced sensitivity.
One of the fundamental limitations of electronic shutters implemented in electronic cameras using advanced CMOS is the need to place the shutter switch in a heavily doped surface well. This requirement stems from the need to isolate the shutter switch from substrate photocurrent. FIG. 2A is a diagram of a semiconductor cross-section of a portion of a CMOS active pixel sensor, showing the effects of failure to provide surface well isolation for the transfer transistor. As shown in FIG. 2A, failure to provide such isolation between the photodiode comprising n+ region 30 in lightly-doped p-type substrate 32, and the n+ source/drain regions 34 and 36 of the transfer transistor allows a leakage path for stray charge carriers (illustrated by the electron designated e− in FIG. 2A) to drift into the n+ source/drain regions 34 and 36 of the transfer transistor.
Several techniques, illustrated in FIGS. 2B and 2C, have been employed to provide a barrier for blocking the leakage currents shown in FIG. 2A. In FIGS. 2B and 2C, structures corresponding to structures illustrated in FIG. 2A will be referred to using the same reference numerals used to identify those structures in FIG. 2A.
FIG. 2B is a diagram of a semiconductor cross-section of a portion of a CMOS active pixel sensor, showing the effects of use of a p-well and p-substrate barrier for isolation of the source/drain regions 34 and 36 of the transfer transistor. For the case shown in FIG. 2B, the transfer transistor is an NMOS device. In FIG. 2B, the n+ source/drain regions 34 and 36 are disposed in p-well 38, doped to about 1e17, a higher doping level than p-type substrate 32, shown doped to a level of about 1e15. The more highly doped p-well region tends to repel the electrons as shown by the curved arrow in FIG. 2B. By repelling electrons, the p-well/p-substrate structure provides a barrier to isolate the source/drain regions 34 and 36 of transfer transistor.
FIG. 2C is a diagram of a semiconductor cross-section of a portion of a CMOS active pixel sensor, showing the effects of use of an n-well barrier for isolation for the transfer transistor. The transfer transistor is now a PMOS device formed in the n-well. In FIG. 2C, the p+ source/drain regions 34 and 36 are disposed in n-well 40, doped to about 1e17. The n-well in FIG. 2C acts as a collection point for the electrons as indicated by the long curved arrow. Electrons are drawn to the positive supply V+ and therefore do not disturb the p+ source/drain regions. In this manner, the n-well structure provides a barrier to isolate the source/drain regions 34 and 36 of the transfer transistor.
NMOS and PMOS surface-well-isolated versions of electronic shutters that are shown in FIGS. 2B and 2C provide isolation from the substrate but the surface wells are required to be more heavily doped than the substrate in order to provide effective isolation and also control of surface concentrations. Furthermore, as CMOS scaling advances, n-wells and p-wells that are available as a natural part of the process become very heavily doped, in the range of 1e17 to 1e18. These high doping levels result in larger electric fields, particularly if signal voltages compatible with competitive imager dynamic range are used. Large electric fields in the shutter switch cause high leakage and low sensitivity as shown in FIG. 1. Because the photodiode charge collection node is to be connected to the electronic switch, the high leakage current and low sensitivity may limit the ability to do high quality long exposures with an electronic shutter of the types shown in FIG. 2. In addition, leakage current is a major source of noise in electronic image sensors, and as such it has a direct impact on dynamic range and image quality for all types of exposures.
Compatibility with advanced CMOS processes, the ability to perform long exposures, better noise and dynamic range performance, as well as eliminating the need for a mechanical shutter in a camera system are all important reasons for an improved electronic shutter technique.